Randstad Verification Engineer in Hillsboro, Oregon

Verification Engineer


Hillsboro, OR

Date Posted:

Thursday, October 13, 2016

Job Type:


Reference #:



Randstad Technologies

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We have a 3 month contract opportunity for a Verification Engineer in Hillsboro, OR. This position will start through the end of 2016 and is intended to extend to July 2017.


· Create pre-silicon verification test plans

· Develop the architecture and design of the verification environment in OVM/UVM

. Develop/run/debug tests and functional coverage in System Verilog

· Mentor other engineers in using the verification infrastructure and creating test benches

Professional Knowledge

· 8+ years of hands-on verification experience using System Verilog and OVM/UVM

. Strong understanding of engineering design principles

· Proven track record in ASIC verification from environment development to tests development

· Excellent written and verbal communication skills

Job Requirements:

· BS in EE or Computer Science, Master?s preferred

· Experience with creation of plans, schedules and cost estimates for design verification efforts

· Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage

· Proficiency in System Verilog

· Experience with OVM/UVM

· Proficiency in scripting languages and utilities including Make, Perl, Python, etc.

· Expert level knowledge of simulation tools such as VCS from Synopsys

· Experience in network ASIC design verification is a plus, (ex: Ethernet, PCI-Express, InfiniBand, SONET)

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